Overview

  • Category: Course Project
  • Course: CPEN 311
  • Time: Jun 2024

Description

This hardware accelerator is written with VHDL and SystemVerilog for the DE1-SoC board. It is highly modular and the number of cores can be reconfigured easily with a change of 1 parameter. Overall, it can decrypt RC4-encrypted 32 byte messages with a 24-bit secret key within 1 second using a 64-core configuration.

Source Code

The code used in this project is stored on GitHub in shihlings/rc4-decoder. Open the repository in GitHub.

Videos

To be added soon.